1. Field of the Invention
Embodiments of the invention relate generally to semiconductor memory devices. More particularly, embodiments of the invention relate to flash memory devices and related operating characteristics.
A claim of priority is made to Korean Patent Application No. 2006-45275 filed on May 19, 2006, the disclosure of which is hereby incorporated by reference.
2. Description of Related Art
Flash memory is a type of nonvolatile semiconductor memory. In recent years, flash memory has become a popular choice for providing data storage in portable electronic devices due, at least in part, to its ability to retain stored data when disconnected from an external power supply, its ability to withstand physical shock, its low power consumption, its relatively high degree of integration, and its relatively low cost.
In general, flash memory can be categorized into different types based on the organization of flash memory cells into different array structures and according to different read/program characteristics. For example, NAND flash memory devices and NOR flash memory devices each have different array structures and different read/program characteristics providing unique tradeoffs and advantages. In particular, NAND flash memory devices tend to have a higher degree of integration, but slower read times, than NOR flash memory devices. Accordingly, NAND flash memory devices are commonly used to provide mass data storage, while NOR flash memory devices are often used to provide storage for data requiring quick access, such as program code.
FIG. 1 is a block diagram illustrating a conventional NAND flash memory device. Referring to FIG. 1, the NAND flash memory device comprises a memory cell array comprising multiple memory blocks (labeled MB(n)). Each memory block comprises a plurality of NAND strings respectively corresponding to columns or bit lines of the NAND flash memory device. As illustrated in FIG. 1, the NAND strings within each memory block are connected to a common source line CSL.
FIG. 2 illustrates NAND strings within a memory block MBi of FIG. 1 in further detail. Referring to FIG. 2, each NAND string comprises a string select transistor SST, a ground select transistor GST, and memory cell transistors MC0 through MC31 connected in series between select transistors SST and GST.
FIG. 3 is a cross sectional view of a memory block MBi shown in FIG. 2. Referring to FIG. 3, memory block MBi is formed inside a pocket P-well 10. Pocket P-well 10 is formed inside a deep N-well 14 on a P-type substrate 12. An example of this triple well structure is disclosed in U.S. Pat. No. 5,962,888 entitled “WELL STRUCTURE NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME”, the disclosure of which is hereby incorporated by reference.
NAND flash memory devices typically perform read and program operations in units of a page, and perform erase operations in units of a memory block. NAND flash memory devices are typically manufactured using complementary metal-oxide semiconductor (CMOS) manufacturing techniques. Semiconductor devices such as positive metal-oxide semiconductor (PMOS) and negative metal-oxide semiconductor (NMOS) transistors constituting peripheral circuits for the NAND flash memory devices are generally formed on a P-type semiconductor substrate.
Unfortunately, where memory cells constituting the memory cell array are formed on a P-type semiconductor substrate without additional processes, a high voltage can not be applied only to a substrate or bulk of the memory cells during an erase operation. Accordingly, the memory cell array is formed in pocket P-well 10, and pocket P-well 10 is formed on deep N-well 14 on P-type substrate 12 using a conventional ion implantation process. During program and read operations, pocket P-well 10 is biased with 0V (e.g., is connected to ground), and during erase operations, pocket P-well 10 is biased with a high voltage such as 20V.
In order to provide a large data storage capacity, the NAND flash memory device must include a large number of memory cells. However, as the number of the memory cells in the device increases, the number of memory cells connected to each row, or the number of strings or bit lines tends to increase. As the number of the strings or bit lines increases, the length of common source line CSL tends to increase accordingly. As the length of common source line CSL increases, resistance in common source line CSL tends to increase as well. Unfortunately, increased resistance in common source line CSL can increase an amount of time required for current to flow through the each NAND string of the NAND flash memory device during read operations. As a result, the lengthening of common source line CSL tends to increase the time required to read data from the NAND flash memory device.
The resistance of common source line CSL can be reduced by a strapping technique. In the strapping technique, metal lines are arranged along common source line CSL and are formed in contact with common source line CSL. The metal lines are called “strapping lines”. An example of the strapping technique is disclosed in U.S. Pat. No. 6,611,460 entitled “NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND PROGRAMMING METHOD THEREOF”, the disclosure of which is hereby incorporated by reference.
Although not illustrated in FIGS. 1 through 3, the strapping lines may be connected to common source line CSL through metal lines connected within dotted ovals “A” and “B” along a dummy bit line DBL illustrated in FIG. 1. Within each memory block in FIG. 1, a dummy string DS is disposed between common source line CSL and a dummy bit line. Although only one dummy string DS is illustrated in each memory block of FIGS. 1 and 2, the number of dummy strings in each memory block can vary according to the number of the bit lines or columns.
In each memory block, dummy string DS has a structure substantially identical to that of the NAND strings. For example, as illustrated in FIG. 2, each dummy string DS typically comprises a string select transistor SST, a ground select transistor GST, and memory cell transistors MC0 through MC31 connected in series between select transistors SST and GST. Transistors SST, GST, and MC0 through MC31 of dummy string DS are connected to signal lines SSL, GSL, and WL0 through WL31, respectively.
The dummy bit line in FIG. 1 is divided into a plurality of dummy bit line segments DBL, where each of dummy bit line segments DBL is arranged across two adjacent memory blocks (e.g., MBi and MB(i+1)). Dummy bit line segments DBL are electrically connected to a power supply line 11 (See, FIG. 2) to supply a well bias voltage VPPWELL for biasing pocket P-well 10. Dummy bit line segments DBL each receive well bias voltage VPPWELL with a fixed level during read, program, and erase operations. Unfortunately, where each dummy bit line segment DBL is connected to well bias voltage VPPWELL, a variety of problems may occur.
As mentioned above, pocket P-well 10 is connected to ground during program and read operations. Where pocket P-well 10 is connected to ground during a program operation, dummy bit line segment DBL is also connected to ground. Where a program voltage Vpgm is applied to word lines connected to memory cells within a dummy string DS during the program operation, those memory cells become programmed. In other words, the threshold voltages of those memory cells is increased.
Unfortunately, where memory cells within a dummy string are programmed, electrons stored in floating gates of those memory cells can affect the threshold voltages of memory cells in adjacent NAND strings due to capacitative coupling. For instance, FIG. 4 illustrates a capacitative interaction between a memory cell in a “normal” NAND string and a memory cell in a “dummy” NAND string. As shown by the threshold voltage diagram at the bottom of FIG. 4, the capacitative interaction can cause the threshold voltage of the memory cell in the normal NAND string to increase as illustrated by a right-pointing arrow. In general, the capacitative interaction can be referred to as “electric field coupling” or “F-poly coupling”. This interaction can cause read failures to occur, especially in devices having relatively small read margins such as multi-bit memory cells.